Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults(Special Section on Discrete Mathematics and Its Applications)

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概要

• 論文の詳細を見る

• The exact expected test lengths of pseudo-random patterns that are generated by LFSRs are theoretically analyzed for a CUT containing hard random-pattern-resistant faults. The exact expected test lengths are also analyzed when more than one primitive polynomials are selected.

• 社団法人電子情報通信学会の論文
• 1998-05-25

著者

• Iwasaki K

  Tokyo Metropolitan Univ. Hachiouji‐shi Jpn

• IWASAKI Kazuhiko

  the Graduate School of Engineering, Tokyo Metroporitan University

• GOTO Hiroyuki

  the Graduate School of Engineering, Chiba University

• Iwasaki Kazuhiko

  The Graduate School Of Engineering Tokyo Metroporitan University

• Goto H

  Japan Res. Inst. Ltd. Tokyo Jpn

関連論文

• Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults(Special Section on Discrete Mathematics and Its Applications)
• Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
• High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
• Deterministic Built-in Test with Neighborhood Pattern Generator

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