Zero Common-Mode Gain Fully Balanced Circuit Structure
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概要
- 論文の詳細を見る
This paper proposes a fully balanced circuit structure with a zero common-mode gain. The common-mode gain of the proposed structure becomes theoretically zero with a perfect device matching. Even if a perfect device matching is not achieved, the common-mode signal can be sufficiently suppressed by the feedback loops provided with the structure. Based on this concept, an integrator is composed. Furthermore the concept can be directly applied to a filter design. The application results in reduced chip area. A design example of a second-order filter and simulation results verify the theoretical expectation.
- 社団法人電子情報通信学会の論文
- 1999-10-25
著者
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藤井 信男
九州大学システム情報科学研究院電気電子システム工学部門
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Takagi S
Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Sato Takuro
Niigata Institute Of Technology
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Sato Takahide
Graduate School Of Science And Engineering Tokyo Institute Of Technology
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FUJII Nobuo
Department of Electrical and Electronic Systems Engineering, Faculty of Information Science and Elec
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TAKAGI Shigetaka
Department of Communications and Integrated Systems, Graduate School of Science and Engineering, Tok
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JEONG Moonjae
Department of Physical Electronics, Tokyo Institute of Technology
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Jeong Moonjae
The Department Of Physical Electronics Tokyo Institute Of Technology
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Sato T
Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Takagi Shigetaka
Department Of Communications And Integrated Systems Graduate School Of Science And Engineering Tokyo
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Fujii Nobuo
Department Of Civil Engineering
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Takagi Shigetaka
Tokyo Inst. Of Technol. Tokyo Jpn
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