A Highly Reliable 0.18μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide
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概要
- 論文の詳細を見る
- 2001-09-25
著者
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IWAMATSU T.
Renesas Technology Corp.
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HIRANO Y.
Process Technology Development Div. Renesas Technology Crop.
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IWAMATSU T.
Process Technology Development Div. Renesas Technology Crop.
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IPPOSHI T.
Process Technology Development Div. Renesas Technology Crop.
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Ipposhi T.
Central Research Laboratory Hitachi Ltd.
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MAEDA S.
ULSI Development Center, Mitsubishi Electric Corporation
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SHIGA K.
ULSI Development Center, Mitsubishi Electric Corporation
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NARUOKA H.
ULSI Development Center, Mitsubishi Electric Corporation
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HATTORI N.
ULSI Development Center, Mitsubishi Electric Corporation
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IWAMATSU T.
ULSI Development Center, Mitsubishi Electric Corporation
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MATSUMOTO T.
ULSI Development Center, Mitsubishi Electric Corporation
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HIRANO Y.
ULSI Development Center, Mitsubishi Electric Corporation
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YAMAGUCHI Y.
ULSI Development Center, Mitsubishi Electric Corporation
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IPPOSHI T.
ULSI Development Center, Mitsubishi Electric Corporation
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MAEGAWA S.
ULSI Development Center, Mitsubishi Electric Corporation
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INUISHI M.
ULSI Development Center, Mitsubishi Electric Corporation
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Inuishi M.
Ulsi Development Center Mitsubishi Electric Corporation
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Maeda S.
Ulsi Development Center Mitsubishi Electric Corporation
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Naruoka H.
Ulsi Development Center Mitsubishi Electric Corporation
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Ishigaki T.
Central Research Laboratory Hitachi Ltd.
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Iwamatsu T.
Ulsi Laboratory Mitsubishi Electric Corporation
関連論文
- Wide-Range V_ Controllable SOTB (Silicon on Thin BOX) Integrated with Bulk CMOS Featuring Fully Silicided NiSi Gate Electrode
- Improvement of Device Characteristics Variation by using a Body-Bias Controlling Technology Based on a Hybrid Trench Isolated SOI
- A Highly Reliable 0.18μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide
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