Substrate Engineering for Reduction of α-Particle-Induced Charge Collection Efficiency
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概要
- 論文の詳細を見る
- 1995-08-21
著者
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Inuishi M.
Process Technology Development Div. Renesas Technology Corp.
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Inuishi M.
Ulsi Development Center Mitsubishi Electric Corporation
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Inuishi M.
Renesas Technology Corp. Wafer Process Engineering Development Dept.
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YAMASHITA T.
ULSI Laboratory, Mitsubishi Electric Corporation
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KOMORI S.
ULSI Laboratory, Mitsubishi Electric Corporation
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KUROI T.
ULSI Laboratory, Mitsubishi Electric Corporation
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HIRAO T.
ULSI Laboratory, Mitsubishi Electric Corporation
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Kuroi T.
Process Technology Development Div. Renesas Technology Corp.
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Kuroi T.
Ulsi Laboratory Mitsubishi Electric Corporation
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Kuroi T.
Process Technology Development Div Renesas Technology Corp.
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KUSUNOKI S.
ULSI Laboratory, Mitsubishi Electric Corporation
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Kusunoki S.
Ulsi Laboratory Mitsubishi Electric Corporation
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Hirao T.
Ulsi Laboratory Mitsubishi Electric Corporation
関連論文
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- Clarification of Floating-Body Effects on Current Drivability in Deep Sub-Quarter Micron Partially-Depleted SOI MOSFET's
- A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond
- Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond
- Substrate Engineering for Reduction of α-Particle-Induced Charge Collection Efficiency
- Layout Independent Transistor with Stress-controlled and Highly Manufacturable STI Process
- Advanced Retrograde Well Technology for 90-nm-node Embedded SRAM by High-Energy Parallel Beam
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