A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond
スポンサーリンク
概要
- 論文の詳細を見る
- 2004-09-15
著者
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Inuishi M.
Process Technology Development Div. Renesas Technology Corp.
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Ohji Y.
Renesas Technology Corp. Wafer Process Engineering Development Dept.
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Inuishi M.
Renesas Technology Corp. Wafer Process Engineering Development Dept.
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ISHIBASHI M.
Process Technology Development Div, Renesas Technology Corp.
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HORITA K.
Process Technology Development Div, Renesas Technology Corp.
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SAWADA M.
Process Technology Development Div, Renesas Technology Corp.
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KITAZAWA M.
Process Technology Development Div, Renesas Technology Corp.
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IGARASHI M.
Process Technology Development Div, Renesas Technology Corp.
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KUROI T.
Process Technology Development Div, Renesas Technology Corp.
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EIMORI T.
Process Technology Development Div, Renesas Technology Corp.
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KOBAYASHI K.
Process Technology Development Div, Renesas Technology Corp.
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OHJI Y.
Process Technology Development Div, Renesas Technology Corp.
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EIMORI T.
Renesas Technology Corp., Wafer Process Engineering Development Dept.
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Kuroi T.
Process Technology Development Div. Renesas Technology Corp.
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Kuroi T.
Process Technology Development Div Renesas Technology Corp.
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Horita K.
Process Technology Development Div. Renesas Technology Corp.
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Kitazawa M.
Process Technology Development Div Renesas Technology Corp.
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Inuishi M.
Process Technology Development Div Renesas Technology Corp.
関連論文
- A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond
- Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond
- Substrate Engineering for Reduction of α-Particle-Induced Charge Collection Efficiency
- Layout Independent Transistor with Stress-controlled and Highly Manufacturable STI Process
- Advanced Retrograde Well Technology for 90-nm-node Embedded SRAM by High-Energy Parallel Beam
- Saturation Phenomenon of Stress Induced Gate Leakage Current
- High Performance 0.2μm Dual Gate CMOS by Suppression of Transient-Enhanced-Diffusion Using Rapid Thermal Annealing Technologies
- Clarification of Nitridation Effect on Oxidation Methods
- Reliability of Non-Uniformly Doped Channel (NUDC) MOSFETs for Sub-Quarter-Micron Region
- Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter Micron LDD MOSFETs
- Impact of Vth interference suppression using a novel Poly Si shield on FLASH memories