Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond
スポンサーリンク
概要
- 論文の詳細を見る
- 2004-09-15
著者
-
Inuishi M.
Process Technology Development Div. Renesas Technology Corp.
-
Ohji Y.
Renesas Technology Corp. Wafer Process Engineering Development Dept.
-
Inuishi M.
Renesas Technology Corp. Wafer Process Engineering Development Dept.
-
HAYASHI T.
Renesas Technology Corp., Wafer Process Engineering Development Dept.
-
YAMASHITA T.
Renesas Technology Corp., Wafer Process Engineering Development Dept.
-
SHIGA K.
Renesas Technology Corp., Wafer Process Engineering Development Dept.
-
HAYASHI K.
Renesas Technology Corp., Wafer Process Engineering Development Dept.
-
ODA H.
Renesas Technology Corp., Wafer Process Engineering Development Dept.
-
EIMORI T.
Renesas Technology Corp., Wafer Process Engineering Development Dept.
-
Eimori T.
Renesas Technology Corp. Wafer Process Engineering Development Dept.
-
Ohji Y.
Renesas Technology Corp.
関連論文
- A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond
- Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond
- Substrate Engineering for Reduction of α-Particle-Induced Charge Collection Efficiency
- Layout Independent Transistor with Stress-controlled and Highly Manufacturable STI Process
- Advanced Retrograde Well Technology for 90-nm-node Embedded SRAM by High-Energy Parallel Beam
- Saturation Phenomenon of Stress Induced Gate Leakage Current
- Clarification of Nitridation Effect on Oxidation Methods
- Reliability of Non-Uniformly Doped Channel (NUDC) MOSFETs for Sub-Quarter-Micron Region
- Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter Micron LDD MOSFETs
- Impact of Vth interference suppression using a novel Poly Si shield on FLASH memories