Layout Independent Transistor with Stress-controlled and Highly Manufacturable STI Process
スポンサーリンク
概要
- 論文の詳細を見る
- 2006-09-13
著者
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INOUE Y.
Process Technology Development Div. Renesas Technology Crop.
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Inuishi M.
Process Technology Development Div. Renesas Technology Corp.
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Inuishi M.
Renesas Technology Corp. Wafer Process Engineering Development Dept.
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ISHIBASHI M.
Process Technology Development Div, Renesas Technology Corp.
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HORITA K.
Process Technology Development Div, Renesas Technology Corp.
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KUROI T.
Process Technology Development Div, Renesas Technology Corp.
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Kuroi T.
Process Technology Development Div. Renesas Technology Corp.
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UMEDA H.
Process Technology Development Div., Renesas Technology Corp.
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KAWAHARA T.
Process Technology Development Div., Renesas Technology Corp.
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IKEDA T.
Process Technology Development Div., Renesas Technology Corp.
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YAMASHITA T.
Process Technology Development Div., Renesas Technology Corp.
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Kuroi T.
Process Technology Development Div Renesas Technology Corp.
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Horita K.
Process Technology Development Div. Renesas Technology Corp.
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Kawahara T.
Process Technology Development Div. Renesas Technology Corp.
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Umeda H.
Process Technology Development Div. Renesas Technology Corp.
関連論文
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- Substrate Engineering for Reduction of α-Particle-Induced Charge Collection Efficiency
- Layout Independent Transistor with Stress-controlled and Highly Manufacturable STI Process
- Advanced Retrograde Well Technology for 90-nm-node Embedded SRAM by High-Energy Parallel Beam
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- High Performance 0.2μm Dual Gate CMOS by Suppression of Transient-Enhanced-Diffusion Using Rapid Thermal Annealing Technologies
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