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Silicon Systems Research Laboratories, NEC Corporation | 論文
- Mechanism of Leakage Current Reduction by Adding WO_3 to Crystallized Ta_2O_5 : Structure and Mechanical and Thermal Properties of Condensed Matter
- Luminescence Centers in Indium-Implanted Silicon
- 70nm MOSFET Device Simulation Considering Two Dimensional Channel Quantization and Self-Consistent Non-Equilibrium Carrier Transport
- Effects of Selecting Channel Direction in Improving Performance of Sub-100nm MOSFETs Fabricated on (110) Surface Si Substrate
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation(High-κ Gate Dielectrics)
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation
- A 0.18-μm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO (Special Issue on Low-Power and High-Speed LSI Technologies)
- Impact of 1-2nm Gate Oxide for Sub-Quarter Micron Dual Gate CMOS
- Application of Fluorinated Amorphous Carbon Thin Films for Low Dielectric Constant Interlayer Dielectrics
- Characteristics of 0.25 μm Ferroelectric Nonvolatile Memory with a Pb(Zr, Ti)O_3 Capacitor on a Metal/Via-Stacked Plug
- 0.25μm FeRAM with CMVP (Capacitor-on-Metal/Via-Stacked-Plug) Memory Cell
- Multilevel Aluminum Dual-Damascene Interconnects for Process-Step Reduction in 0.18 μm ULSIs
- Multilevel Aluminum Dual-Damascene Interconnects (Al-DDI) for Process-Step Reduction in 0.18um-ULSIs
- Effects of Discharge Frequency in Plasma Etching and Ultrahigh-Frequency Plasma Source for High-Performance Etching for Ultralarge-Scale Integrated Circuits
- 0.15μm CMOS Devices with Reduced Junction Capacitance
- Electrical Characteristics of SrBi_2Ta_2O_9 Capacitor after Aluminum Metallization
- Ultralow-Voltage MTCMOS/SOI Circuits for Batteryless Mobile System(Low-Power System LSI, IP and Related Technologies)
- Ultrathin Oxide Film Formation Using Radical Oxygen in an Ultrahigh Vacuum System
- A 1.5V, 8mW, 8b, 15Msps BiCMOS A/D Converter (Special Section on Analog Circuit Techniques and Related Topics)
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs