Effects of Selecting Channel Direction in Improving Performance of Sub-100nm MOSFETs Fabricated on (110) Surface Si Substrate
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-04-30
著者
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EZAKI Tatsuya
Silicon Systems Research Laboratories, NEC Corporation
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HANE Masami
Silicon Systems Research Laboratories, NEC Corporation
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NAKAMURA Hidetatsu
Silicon Systems Research Labs., NEC Corporation
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IWAMOTO Toshiyuki
Silicon Systems Research Labs., NEC Corporation
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TOGO Mitsuhiro
Silicon Systems Research Labs., NEC Corporation
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IKEZAWA Takeo
Platform Software Division, NEC Infomatec Systems, Ltd.
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IKARASHI Nobuyuki
Silicon Systems Research Labs., NEC Corporation
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YAMAMOTO Toyoji
Silicon Systems Research Labs., NEC Corporation
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Hane Masami
Silicon Systems Research Labs. Nec Corporation
関連論文
- 70nm MOSFET Device Simulation Considering Two Dimensional Channel Quantization and Self-Consistent Non-Equilibrium Carrier Transport
- Effects of Selecting Channel Direction in Improving Performance of Sub-100nm MOSFETs Fabricated on (110) Surface Si Substrate
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation(High-κ Gate Dielectrics)
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation
- Impact of 1-2nm Gate Oxide for Sub-Quarter Micron Dual Gate CMOS
- Three Dimensional MOSFET Simulation for Analyzing Statistical Dopant-Induced Fluctuations Associated with Atomistic Process Simulator(the IEEE International Coference on SISPAD '02)
- First observation of SiO_2/Si(100) interfaces by spherical aberration-corrected high-resolution transmission electron microscopy
- Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate