Impact of 1-2nm Gate Oxide for Sub-Quarter Micron Dual Gate CMOS

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概要

• 論文の詳細を見る
• 1999-09-20

著者

• YAMAMOTO Toyoji

  Silicon Systems Research Labs., NEC Corporation

• Uejima Kazuya

  Silicon Systems Research Laboratories Nec Corporation

• MOGAMI Tohru

  Silicon Systems Research Laboratories, NEC Corporation

• Mogami Tohru

  Silicon Systems Research Laboratories Nec Corporation

• Yamamoto Toyoji

  Silicon Systems Research Laboratories Nec Corporation

関連論文

• Effects of Selecting Channel Direction in Improving Performance of Sub-100nm MOSFETs Fabricated on (110) Surface Si Substrate
• Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation(High-κ Gate Dielectrics)
• Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation
• Impact of 1-2nm Gate Oxide for Sub-Quarter Micron Dual Gate CMOS
• Ultralow-Voltage MTCMOS/SOI Circuits for Batteryless Mobile System(Low-Power System LSI, IP and Related Technologies)
• ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
• ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
• Uniform Raised-Salicide Technology for High-Performance CMOS Devices(Special Issue on Advanced Sub-0.1μm CMOS Devices)
• The Influence of the Device Miniaturization on the I_ Enhancement in the Intrinsic Silicon Body (i-body) SOI-MOSFET's
• A Study of the V_ Fluctuation for 25nm CMOS
• Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate

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