Three Dimensional MOSFET Simulation for Analyzing Statistical Dopant-Induced Fluctuations Associated with Atomistic Process Simulator(<Special Issue>the IEEE International Coference on SISPAD '02)
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概要
- 論文の詳細を見る
A realistic 3-D process/device simulation method was developed for investigating the fluctuation in device characteristics induced by the statistical nature of the number and position of discrete dopant atoms. Monte Carlo procedures are applied for both ion implantation and dopant diffusion/activation simulations. Atomistic potential profile for device simulation is calculated from discrete dopant atom positions by incorporating the long-range part of Coulomb potential. This simulation was used to investigate the variations in characteristics of sub-100 nm CMOS devices induced by realistic dopant fluctuations considering practical device fabrication processes. In particular, sensitivity analysis of the threshold voltage fluctuation was performed in terms of the independent dopant contribution, such as that of the dopant in the source/drain or channel region.
- 社団法人電子情報通信学会の論文
- 2003-03-01
著者
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EZAKI Tatsuya
Silicon Systems Research Laboratories, NEC Corporation
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Hane Masami
Silicon Systems Research Laboratories Nec Corporation
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Ezaki Tatsuya
Silicon Systems Research Laboratories Nec Corporation
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Ezaki T
Tokyo Univ. Sci. Noda‐shi Jpn
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IKEZAWA Takeo
NEC Infomatec Systems Ltd.
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NOTSU Akio
NEC Infomatec Systems Ltd.
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TANAKA Katsuhiko
Silicon Systems Research Laboratories,NEC Corporation
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Tanaka Katsuhiko
Silicon Systems Research Laboratories Nec Corporation
関連論文
- 70nm MOSFET Device Simulation Considering Two Dimensional Channel Quantization and Self-Consistent Non-Equilibrium Carrier Transport
- Effects of Selecting Channel Direction in Improving Performance of Sub-100nm MOSFETs Fabricated on (110) Surface Si Substrate
- Three Dimensional MOSFET Simulation for Analyzing Statistical Dopant-Induced Fluctuations Associated with Atomistic Process Simulator(the IEEE International Coference on SISPAD '02)
- Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate