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Silicon Systems Research Laboratories, NEC Corporation | 論文
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- Uniform Raised-Salicide Technology for High-Performance CMOS Devices(Special Issue on Advanced Sub-0.1μm CMOS Devices)
- Uniform Si-SEG and Ti/SEG-Si Thickness Ratio Control for Ti-Salicided Sub-Quarter-Micron CMOS Devices
- Three Dimensional MOSFET Simulation for Analyzing Statistical Dopant-Induced Fluctuations Associated with Atomistic Process Simulator(the IEEE International Coference on SISPAD '02)
- The Influence of the Device Miniaturization on the I_ Enhancement in the Intrinsic Silicon Body (i-body) SOI-MOSFET's
- A Study of the V_ Fluctuation for 25nm CMOS
- Effects of Degree of Dissociation on Aluminum Etching in High-Density Cl_2 Plasmas
- Quantitative Characterization of Roughness at SiO_2/Si Interfaces by Using Cross-sectional High-resolution Transmission Electron Microscopy
- Potential of MRAM and Technological Challenges
- Comparison of Iron Gettering Effectiveness in Silicon between Ion-Implantation-Induced Damage and Poly-Crystalline Silicon
- Formation of Buried Oxide Layer in Si Substrates by Oxygen Precipitation at Implantation Damage of Light Ions
- Oxygen Precipitates and Related Defects in SOI Substrate Fabricated by Wafer Bonding and H^+ Splitting