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Renesas Technology Corporation | 論文
- Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications(Special Issue on High-Performance and Low-Power Microprocessors)
- A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
- A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
- Impact of Self-Heating in Wire Interconnection on Timing
- An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
- Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
- A Method to Derive SSO Design Rule Considering Jitter Constraint(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design(Prediction and Analysis, VLSI Design and CAD Algorithms)
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
- On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform
- A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design(Novel Device Architectures and System Integration Technologies)
- Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
- Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
- A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
- Multimedia Accelerator ACE : A Practical Approach for Multimedia Applications
- Effect of Compensation Implant in SONOS Flash EEPROMs