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Renesas Technology Corporation | 論文
- Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
- A 300MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers
- A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme
- A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
- A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
- A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model
- A 126mm^2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology(Integrated Electronics)
- An Embedded DRAM Hybrid Macro with Auto Signa Management and Enhanced-on-Chip Tester
- A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
- A Fast Characterizing Method for Large Embedded Memory Modules on SoC(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures(Interconnect, VLSI Design and CAD Algorithms)
- Absorption Coefficient Measurements of MgZnCdSe II-VI Compounds on InP Substrates and Quantum Confined Stark Effect in ZnCdSe/MgZnCdSe Multiple Quantum Wells
- Absorption Coefficient Measurements of MgZnCdSe II-VI Compounds on InP Substrates and Quantum Confined Stark Effect in ZnCdSe/MgZnCdSe Multiple Quantum Wells
- Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
- センス同期式書き込み/読出し方式回路を搭載したSRAM I/F混載DRAMコア(MRAM,不揮発メモリ,メモリ,一般)
- A Low-Power Microcontroller with Body-Tied SOI Technology(Low-Power System LSI, IP and Related Technologies)
- Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation(the IEEE International Conference on SISPAD '02)
- Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
- A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology