A 126mm^2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology(Integrated Electronics)

概要

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A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layerbit-line technology combined with a multilevel cell technique achieved a bit area 2F^2 of 0.0162μm^2, resulting in a chip size of 126mm^2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10MB/s.
社団法人電子情報通信学会の論文
2007-11-01