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Renesas Technology Corporation | 論文
- A 300MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers
- A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
- A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(VLSI Design and CAD Algorithms)
- A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
- Novel VLIW Code Compaction Method for a 3D Geometry Processor
- A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors(Low-Power System LSI, IP and Related Technologies)
- Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
- A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
- Investigation of Hall Resistivity in Antidot Lattices with respect to Commensurability Oscillations
- On the Mechanism of Commensurability Oscillations in Anisotropic Antidot Lattices
- Current-Direction-Dependent Commensurate Oscillations in GaAs/AlGaAs Antidot Superlattice
- 招待講演 A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and E-trim fuse for known good die (集積回路)
- A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- An Exact Leading Non-Zero Detector for a Floating-Point Unit(Digital, Low-Power LSI and Low-Power IP)
- A 4500 MIPS/W, 86μA Resume-Standby, 11μA Ultra-Standby Application Processor for 3G Cellular Phones(Digital, Low-Power LSI and Low-Power IP)
- An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU(System Level Design)(VLSI Design and CAD Algorithms)