A 4500 MIPS/W, 86μA Resume-Standby, 11μA Ultra-Standby Application Processor for 3G Cellular Phones(Digital, <Special Section>Low-Power LSI and Low-Power IP)
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概要
- 論文の詳細を見る
We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. For low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointerbased pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at 1.0 V power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through μI/O circuits to prevent invalid signal transmission. In the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In the U-standby mode, the power supply to the URAM is also turned off for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12μA. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully recover from R-standby.
- 社団法人電子情報通信学会の論文
- 2005-04-01
著者
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石川 誠
東京工業大学 工学部
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石川 誠
(株)日立製作所中央研究所
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Nishii Osamu
Renesas Technology Corp.
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Furuyama Mikio
Renesas Technology Corporation
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Hayashi T
Superh Japan Ltd.
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ARAKAWA Fumio
Central Research Laboratory, Hitachi, Ltd.
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ISHIKAWA Makoto
Central Research Laboratory, Hitachi, Ltd.
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KAMEI Tatsuya
Renesas Technology Corporation
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KONDO Yuki
Central Research Laboratory, Hitachi, Ltd.
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YAMAOKA Masanao
Central Research Laboratory, Hitachi, Ltd.
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SHIMAZAKI Yasuhisa
SuperH (Japan) Ltd.
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OZAWA Motokazu
Central Research Laboratory, Hitachi, Ltd.
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TAMAKI Saneaki
Renesas Technology Corporation
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HOSHI Tadashi
Renesas Technology Corporation
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NISHII Osamu
SuperH (Japan) Ltd.
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HIROSE Kenji
Renesas Technology Corporation
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YOSHIOKA Shinichi
Renesas Technology Corporation
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HATTORI Toshihiro
Renesas Technology Corporation
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Ishikawa Makoto
Hitachi America Ltd. Mi Usa
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Arakawa Fumio
Hitachi Ltd.
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Arakawa Fumio
Central Research Laboratory Hitachi Ltd.
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Tamaki Saneaki
Semiconductor & Integrated Circuits Hitachi Ltd.
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Ozawa Motokazu
Hitachi Ltd.
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Yamaoka Masanao
Hitachi Ltd. Kokubunji‐shi Jpn
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Yamaoka Masanao
Central Research Laboratory Hitachi Ltd.
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Hoshi Tadashi
Renesas Technology Corp.
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Hattori Toshihiro
Renesas Technology
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Kondo Yuki
Central Research Laboratory Hitachi Ltd.
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Hayashi Tomoichi
Superh Japan Ltd.
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Ishikawa Makoto
Automotive Products Laboratory Hitachi America. Ltd.:(present Office)central Research Laboratory Hit
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