An Exact Leading Non-Zero Detector for a Floating-Point Unit(Digital, <Special Section>Low-Power LSI and Low-Power IP)
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概要
- 論文の詳細を見る
Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.
- 社団法人電子情報通信学会の論文
- 2005-04-01
著者
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Hayashi T
Superh Japan Ltd.
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ARAKAWA Fumio
Central Research Laboratory, Hitachi, Ltd.
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HAYASHI Tomoichi
SuperH Japan, Ltd.
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NISHIBORI Masakazu
Renesas Technology Corporation
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Arakawa Fumio
Hitachi Ltd.
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Arakawa Fumio
Central Research Laboratory Hitachi Ltd.
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Hayashi Tomoichi
Superh Japan Ltd.
関連論文
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