An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU(System Level Design)(<Special Section>VLSI Design and CAD Algorithms)

概要

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A SuperH^<TM> embedded processor core implemented in a 130-nm CMOS process running at 400MHz achieved 720MIPS and 2.8 GFLOPS at a power of 250mW in worst-case conditions. It has a dualissue seven-stage pipeline architecture but maintains the 1.8 MIPS/MHz of the previous five-stage processor. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.
社団法人電子情報通信学会の論文
2004-12-01