A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor(<Special Section>Low-Power System LSI, IP and Related Technologies)

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概要

• 論文の詳細を見る

• In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200MHz only with 80mW at 1.0V, namely 4500MIPS/W and 4.2mA leakage current without any power-cut mode.

• 社団法人電子情報通信学会の論文
• 2004-04-01

著者

• OGURA Kenji

  Hitachi ULSI Systems Co., Ltd.

• Hattori Toshihiro

  Renesas Technology Corp.

• Hattori Toshihiro

  Renesas Technology

• Ogura Kenji

  Hitachi Ulsi Systems Co. Ltd.

関連論文

• A 4500 MIPS/W, 86μA Resume-Standby, 11μA Ultra-Standby Application Processor for 3G Cellular Phones(Digital, Low-Power LSI and Low-Power IP)
• Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
• Multi-Core/Multi-IP Technology for Embedded Applications
• Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor(Low-Power System LSI, IP and Related Technologies)

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