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Renesas Technology Corp. | 論文
- An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment
- Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications(Integrated Electronics)
- 周期的電荷排出動作を用いた Time-of-Flight 距離画像センサの背景光下における距離分解能に関する実験的検証
- 書き込みマージンを増加させた低電力SoC向け混載SRAM(新メモリ技術, メモリ応用技術, 一般, ISSCC特集1 SRAM)
- A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
- A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(VLSI Design and CAD Algorithms)
- A Sub 1-V L-Band Low Noise Amplifier SOI CMOS(Special Section on Analog Circuit Techniques and Related Topics)
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
- High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
- Deterministic Built-in Test with Neighborhood Pattern Generator
- A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
- Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
- Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
- Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
- Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- A GFSK Transmitter Architecture for a Bluetooth RF-IC, Featuring a Variable-Loop-Bandwidth Phase-Locked Loop Modulator(Microwaves, Millimeter-Waves)
- A Small-Chip-Area Transceiver IC for Bluetooth Featuring a Digital Channel-Selection Filter(Analog Circuit and Device Technologies)