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Imec | 論文
- Reliability of Ultra-Thin Gate Oxide Below 3 nm in the Direct Tunneling Regime
- Reliability of Ultra-Thin Gate Oxides Below 3nm in the Direct Tunneling Regime
- 21.3:The Design and Fabrication of a 2560×2048 Pixel Microdisplay Chip(2.発表概要)(Report on IDRC'99(EuroDisplay'99)
- Practical Solutions to Enhance EWF Tunability of Ni FUSI Gates on HfO_2
- Highly Manufacturable CMOSFETs with Single High-k (HfLaO) and Dual Metal Gate Integration Process
- A Novel Dual-Metal Gate Integration Process for Sub-1nm EOT HfO_2 CMOS Devices
- Impact of Radiation-Induced Back-Channel Leakage and Back-Gate Bias on Drain Current Transients of Thin-Gate-Oxide Partially Depleted Silicon-On-Insulator n-channel Metal-Oxide-Semiconductor Field-Effect Transistors
- Deep Levels in High-Temperature 1 MeV Electron-Irradiated n-Type Czochralski Silicon
- A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs
- A Static Model for Scratches Generated during Aluminum Chemical-Mechanical Polishing Process : Orbital Technology
- Integration of ultra shallow junctions in PVD TaN nMOS transistors with Flash Lamp Annealing
- Degradation and Breakdown of Sub-1nm EOT HfO_2/Metal Gate Stacks
- Degradation and Breakdown of Sub-1nm EOT HfO_2/Metal Gate Stacks
- Reliability Issues in High-k Stacks
- Failure Rate Prediction and Accelerated Detection of Anomalous Charge Loss in Flash Memories by Using an Analytical Transient Physics-Based Charge Loss Model
- Time Dependent Anomalous Charge Loss Modeling in Flash Memories and an Accelerated Testing Procedure
- A CMOS DC Voltage Doubler with Nonoverlapping Switching Control
- Integrating Diffusionless Anneals Into Advanced CMOS Technologies
- Study of Dopant Diffusion and Defect Evolution for Advanced Ultra Shallow Junctions based on Atomistic Modeling
- Investigation and Comparison of the Noise in the Gate and Substrate Current after Soft-Breakdown