Reliability of Ultra-Thin Gate Oxides Below 3nm in the Direct Tunneling Regime
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概要
- 論文の詳細を見る
- 1996-08-26
著者
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HEYNS Marc
IMEC
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Degraeve Robin
Imec
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Depas Michel
Imec Vzw
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Heyns Marc
Interuniversity Microelectronics Centre
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Nigam Tanya
Imec
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Heyns M
Imec Leuven Bel
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GROESENEKEN Guido
IMEC
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DEPAS Michel
Interuniversity Microelectronics Centre
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Depas Michel
IMEC
関連論文
- Atomic Force Microscopy and Infrared Spectroscopy Studies of Hydrogen Baked Si Surfaces
- Current-Voltage Characteristics of Gate Oxides after Hard Breakdown
- Morphology Change of Artificial Crystal Originated Particles, and the Effect on Gate Oxide Integrity
- Breakdown and Recovery of Thin Gate Oxides
- Fabrication and Characterization of Artificial Crystal Originated Particles
- Impact of Organic Contamination on Thin Gate Oxide Quality
- H_2O_2 Decomposition and Its Impact on Silicon Surface Roughening and Gate Oxide Integrity
- Charge Trapping in SiO_x/ZrO_2 and SiO_x/TiO_2 Gate Dielectric Stacks
- Critical Parameters for Obtaining Low Particle Densities on a Si Surface in an HF-Last Process
- Gate Voltage Dependence of Reliability for Ultra-Thin Oxides
- Reliability of Ultra-Thin Gate Oxide Below 3 nm in the Direct Tunneling Regime
- Reliability of Ultra-Thin Gate Oxides Below 3nm in the Direct Tunneling Regime
- Investigation and Comparison of the Noise in the Gate and Substrate Current after Soft-Breakdown
- Reliability of Ultra-Thin Gate Oxide Below 3 nm in the Direct Tunneling Regime