HEYNS Marc | IMEC
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概要
関連著者
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HEYNS Marc
IMEC
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Heyns Marc
Interuniversity Microelectronics Centre
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Heyns M
Imec Leuven Bel
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Degraeve Robin
Imec
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Depas Michel
Imec Vzw
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Nigam Tanya
Imec
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GROESENEKEN Guido
IMEC
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DEPAS Michel
Interuniversity Microelectronics Centre
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MERTENS Paul
IMEC
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Depas Michel
IMEC
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Chollet F
Univ. Franche‐comte Besancon Fra
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Bender H
Imec Leuven Bel
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VATEL Olivier
IMEC
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VERHAVERBEKE Steven
IMEC
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BENDER Hugo
IMEC
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CAYMAX Matty
IMEC
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CHOLLET Frederic
CNET
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VERMEIRE Bert
IMEC
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ANDRE Elie
CNET
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Hatcher Zach
Ashland Chemical
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Andre E
France Telecom Meylan Fra
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Mertens P
Interuniversity Microelectronics Center
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Verhaverbeke S
Imec Kapeldreef
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Heyns M
Interuniv. Microelectronics Center Leuven Bel
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Alay Josep-lluis
Imec Kapeldreef : Lcmm Universitat De Barcelona
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Vatel Olivier
Centre National D'etudes Des Telecommunications
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MEURIS Marc
IMEC vzw
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Schmidt Harald
IMEC
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Rotondaro Antonio
IMEC
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Hurd Trace
Texas Instruments
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Houssa Michel
Department Of Physics Katholieke Universiteit Leuven
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NAILI Mohamed
IMEC
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STESMANS Andre
Department of Physics, Katholieke Universiteit Leuven
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ALAY Josep-Lluis
IMEC, Kapeldreef
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VERHAVERBEKE Steven
IMEC, Kapeldreef
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VANDERVORST Wilfried
IMEC, Kapeldreef
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HEYNS Marc
IMEC, Kapeldreef
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DEGRAEVE Robin
Interuniversity Microelectronics Centre
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NIGAM Tanya
Interuniversity Microelectronics Centre
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GROESENEKEN Guido
Interuniversity Microelectronics Centre
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Vandervorst W
Insys Leuven Bel
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Hurd Trace
Texas Instruments:(present Address)imec
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Meuris Marc
Imec
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Heyns Marc
Interuniversitary Micro-Electronics Center
著作論文
- Atomic Force Microscopy and Infrared Spectroscopy Studies of Hydrogen Baked Si Surfaces
- H_2O_2 Decomposition and Its Impact on Silicon Surface Roughening and Gate Oxide Integrity
- Charge Trapping in SiO_x/ZrO_2 and SiO_x/TiO_2 Gate Dielectric Stacks
- Critical Parameters for Obtaining Low Particle Densities on a Si Surface in an HF-Last Process
- Gate Voltage Dependence of Reliability for Ultra-Thin Oxides
- Reliability of Ultra-Thin Gate Oxide Below 3 nm in the Direct Tunneling Regime
- Reliability of Ultra-Thin Gate Oxides Below 3nm in the Direct Tunneling Regime