A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs
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概要
- 論文の詳細を見る
A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5µW at 1.8V power supply and 1GHz clock frequency.
- （社）電子情報通信学会の論文
- 2009-10-01
著者
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VAN DER
IMEC
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Vandewege Jan
Ghent University
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YIN Xin
Ghent University
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TORFS Guy
Department of Information Technology of Ghent University
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LI Zhisheng
Department of Information Technology of Ghent University
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BAUWELINCK Johan
Department of Information Technology of Ghent University
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YIN Xin
Department of Information Technology of Ghent University
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VANDEWEGE Jan
Department of Information Technology of Ghent University
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Bauwelinck Johan
Ghent University
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