A 0.5-V Six-Transistor Static Random Access Memory with Ferroelectric-Gate Field Effect Transistors

概要

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A 0.5 V six-transistor static random access memory (6T-SRAM) with ferroelectric-gate field-effect-transistors (Fe-FETs) is proposed and experimentally demonstrated for the first time. During the read and the hold, the threshold voltage ($V_{\text{TH}}$) of Fe-FETs automatically changes to increase the static noise margin (SNM) by 60%. During the stand-by, the $V_{\text{TH}}$ of the proposed SRAM cell increases to decrease the leakage current by 42%. In case of the read, the $V_{\text{TH}}$ of the read transistor decreases and increases the cell read current to achieve the fast read. During the write, the $V_{\text{TH}}$ of the SRAM cell dynamically changes and assist the cell data to flip, realizing a write assist function. The enlarged SNM realizes the $V_{\text{DD}}$ reduction by 0.11 V, which decreases the active power by 32%. The proposed SRAM layout is the same as the conventional 6T-SRAM and there is no area penalty.
2010-12-25