3x Write and 5x Read Speed Increase for RRAM with Disturb Free Bipolar Operation
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概要
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In recent years, sensor network has attracted much attention in agricultural, medical, and disaster-prevention area to collect on-field information. Each sensor node requires extremely low-power operation because its battery size is limited. In the sensor node chip, memory consumes large leakage power so a low-power memory technique is strongly required.<br /><br /> This paper presents a novel low-power technique for a ferroelectric 6T4C shadow SRAM. The shadow SRAM works a high-speed SRAM in an active mode and a nonvolatile FeRAM in a sleep mode. The nonvolatility completely removes the leakage current from the memory. However, the ferroelectric capacitors increase the power consumption and decrease the cycle time of the SRAM. In this paper, the proposed technique is evaluated by SPICE simulation results.
- 2012-12-10
著者
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Takeuchi Ken
Department of Electrical Engineering and Information Systems, Chuo University, Bunkyo, Tokyo 112-8551, Japan
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Ning Sheyang
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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OGURA IWASAKI
Department of Electrical, Electronic, and Communication Engineering, Faculty of Science and Engineering, Chuo University
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NING Sheyang
Department of Electrical, Electronic, and Communication Engineering, Faculty of Science and Engineering, Chuo University:Department of Electrical Engineering and Information Systems, Graduate School of Engineering, University of Tokyo
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- 3x Write and 5x Read Speed Increase for RRAM with Disturb Free Bipolar Operation