A Negative Word-Line Voltage Negatively-Incremental Erase Pulse Scheme with $\Delta V_{\text{TH}} = 1/6\Delta V_{\text{ERASE}}$ for Enterprise Solid-State Drive Application Ferroelectric-NAND Flash Memories

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概要

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• A negative word-line voltage negatively-incremental erase pulse scheme is proposed for the enterprise solid-state drive (SSD) application ferroelectric (Fe)-NAND flash memories. The negative word-line voltage erase accelerates the erase pulse ramp-up from 1 ms of the conventional well erase to 2 μs and a 200 μs/page erase is realized. The erase characteristics with various erase pulse shape such as the fixed erase pulse, the variable time erase pulse, and the proposed negatively-incremental erase pulse for the Fe-NAND cells are investigated. With the proposed scheme, the erase voltage, $V_{\text{ERASE}}$ decreases by $\Delta V_{\text{ERASE}}$. The measured $V_{\text{TH}}$ shift, $\Delta V_{\text{TH}}$, is constant at $1/6\Delta V_{\text{ERASE}}$, which is different from that of the floating-gate NAND cells where $\Delta V_{\text{TH}} = \Delta V_{\text{ERASE}}$. The mechanism of the constant $\Delta V_{\text{TH}}$ is discussed with the major and the minor polarization–electric field curves. By combining the proposed negatively-incremental erase scheme with the bit-by-bit verify, a narrow erase $V_{\text{TH}}$ distribution of 0.07 V is achieved with $\Delta V_{\text{ERASE}}$ of 0.4 V.

• 2010-04-25

著者

• Takahashi Mitsue

  National Inst. Of Advanced Industrial Sci. And Technol.

• Ken Takeuchi

  Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan

• Hatanaka Teruyoshi

  Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan

• Yajima Ryoji

  Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan

• Shigeki Sakai

  National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

関連論文

• A Negative Word-Line Voltage Negatively-Incremental Erase Pulse Scheme with $\Delta V_{\text{TH}} = 1/6\Delta V_{\text{ERASE}}$ for Enterprise Solid-State Drive Application Ferroelectric-NAND Flash Memories
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