Advantages of Densely Packed Multi-Wire Transistors with Planar Gate Structure Fabricated on Low-$k$ Buried Insulator over Planar Silicon-on-Insulator Devices
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概要
- 論文の詳細を見る
In this paper, electrical characteristics of densely packed multi wire transistors with a planar gate structure are systematically investigated using three-dimensional device simulations in terms of dependences of threshold voltage roll-off and current drivability on a channel width, height, and distance. The simulation results revealed that densely packed multi wire transistors with a planar gate structure have advantages over planar silicon-on-insulator (SOI) devices in terms of both threshold voltage roll-off characteristics and current drivability. It is shown that narrowing a width and lowering a height of channels are effective for improvement in both threshold voltage roll-off characteristics and current drivability and that shrinking a distance between channels is effective for improvement in current drivability although it degrades threshold voltage roll-off characteristics. It is also shown that lowering a dielectric constant of a buried insulator below wires is effective for improvement in both threshold voltage roll-off characteristics and current drivability of wire transistors.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2009-05-25
著者
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Ono Mizuki
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Uchida Ken
Department Of Biology Faculty Of Science Kumamoto University
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Tezuka Tsutomu
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 1 Komukai-Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan
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Ono Mizuki
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 1 Komukai-Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan
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