Fabrication of 50 nm Trigate Silicon On Insulator Metal–Oxide–Silicon Field-Effect Transistor without Source/Drain Activation Annealing

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This paper presents the electrical characteristics of trigate silicon-on-insulator (SOI) n-type metal–oxide–silicon field-effect transistor (n-MOSFET) devices with a gate length of 50 nm, a channel width of 100 nm, and a channel thickness of 30 nm. The source and drain of these trigate SOI n-MOSFETs were formed by ion-shower doping at 250°C. In particular, activation annealing after ion-shower doping was excluded in order to improve the lateral steepness of the source/drain junction. Without any additional thermal processes, a low sheet resistance ($R_{\text{s}}$) of 1.2 k$\Omega$/$\square$ was obtained by ion-shower doping, and trigate MOSFETs showed satisfactory electrical characteristics. Since the short-channel effect was suppressed and the ratio of maximum drain current to minimum drain current ($I_{\text{max}}/I_{\text{min}}$) as ${\sim}10^{5}$, it is thought that the ion-shower doping process is effective for fabricating short-channel trigate SOI MOSFET devices.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2004-05-15