Gate Voltage Reduction of a Ferroelectric Gate Field-Effect Transistor Memory with an Intermediate Electrode on Data-Reading
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概要
- 論文の詳細を見る
We introduce a new ferroelectric gate field-effect transistor (FeFET) memory with an intermediate electrode for data-writing inserted between a ferroelectric capacitor and a metal-oxide-semiconductor (MOS) field-effect transistor (FET). This memory requires another FET (W-FET) to short the gate of the MOSFET electrically for data-writing. For data-reading, although the W-FET is in the off state, a leakage current flows through the W-FET due to the application of a reading voltage to the ferroelectric capacitor and MOSFET in series. The leakage current reduces the gate voltage of the MOSFET, which leads to low endurance of the reading cycle. We propose one method to suppress the leakage current and to improve the endurance.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 2003-04-01
著者
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Horita Susumu
School Of Materials Science Japan Advanced Institute Of Science And Technology
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Khoa Tran
School Of Materials Science Japan Advanced Institute Of Science And Technology
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Khoa Tran
School of Materials Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Tatsunokuchi, Ishikawa 923-1292, Japan
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