A-3-10 Top Layer Plating Lead Maximization for BGA Packages
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概要
- 論文の詳細を見る
- 2009-09-01
著者
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TOMIOKA Yoichi
Department of Communications and Integrated Systems, Tokyo Institute of Technology
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Takahashi Atsushi
Division of Electrical, Electronic and Information Engineering, Osaka University
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Tomioka Yoichi
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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Takahashi Atsushi
Division Of Electrical Electronic And Information Engineering Osaka University
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Takahashi Atsushi
Graduate School Of Engineering Osaka University
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Takahashi Atsushi
Faculty of Engineering, Tokyo Institute of Technology
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Takahashi Atsushi
Division Of Electrical Electronic And Information Engineering Graduate School Of Engineering Osaka University
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- FOREWORD
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