Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion (Special Section on VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. In a semi-synchronous circuit, the minimum delay between registers may be critical with respect to the clock period of the circuit, while it does not affect the clock period of an ordinary synchronous circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio over the cycles in the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposing gate-level delay insertion method.
- 一般社団法人電子情報通信学会の論文
- 1999-11-25
著者
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Takahashi Atsushi
Department Of Cardiology Akita City General Hospital
-
Takahashi Atsushi
Graduate School Of Engineering Osaka University
-
Yoda T
Tokyo Inst. Technol. Tokyo Jpn
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YODA Tomoyuki
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
-
Takahashi Atsushi
Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
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Takahashi Atsushi
Departmant Of Surgery(i) Kanazawa University School Of Medicine
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