Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
スポンサーリンク
概要
- 論文の詳細を見る
In multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on a selection of inter-FPGA signals to be time-multiplexed. In this paper, we propose a method that minimizes the verification time of multi-FPGA systems by finding an optimal selection of inter-FPGA signals to be time-multiplexed. In the experiments, it is shown that the estimated verification time is improved 38.2% on average compared with conventional methods.
- （社）電子情報通信学会の論文
- 2008-12-01
著者
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Takahashi Atsushi
Department of Cardiology, Yokosuka Kyosai Hospital
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Takashima Yasuhiro
Faculty Of Environmental Engineering The University Of Kitakyushu
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Takashima Yasuhiro
The Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
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Takahashi Atsushi
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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Takashima Yasuhiro
Univ. Kitakyushu Kitakyushu‐shi Jpn
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Takahashi Atsushi
Department Of Cardiology Akita City General Hospital
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Takahashi Atsushi
Graduate School Of Engineering Osaka University
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Takahashi Atsushi
Faculty of Engineering, Tokyo Institute of Technology
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INAGI Masato
Graduate School of Information Sciences, Hiroshima City University
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NAKAMURA Yuichi
System IP Core Research Laboratories, NEC
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Inagi Masato
Graduate School Of Information Sciences Hiroshima City University
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Nakamura Yuichi
System Ip Core Research Laboratories Nec
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Nakamura Yuichi
System Ip Core Research Lab. Nec
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Takahashi Atsushi
Departmant Of Surgery(i) Kanazawa University School Of Medicine
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Nakamura Yuichi
System Ip Core Res. Laboratories Nec Corp.
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