The Oct-Touched Tile : A New Architecture for Shape-Based Routing(<Special Section> Analog Circuit Techniques and Related Topics)
スポンサーリンク
概要
- 論文の詳細を見る
The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, path finding and shape-based sizing are executed on the same architecture. In experiments, our system demonstrates the performance comparable to a commercial tool. In addition, we show potential of OTT by introducing several ideas of extensions to analog layout constraints.
- 社団法人電子情報通信学会の論文
- 2006-02-01
著者
-
Takashima Yasuhiro
The Department Of Information And Media The University Of Kitakyushu
-
Takashima Yasuhiro
The Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
Nakatake S
The Department Of Information And Media The University Of Kitakyushu
-
Kajitani Y
Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
Kajitani Yoji
The Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
FU Ning
the Department of Information and Media, the University of Kitakyushu
-
NAKATAKE Shigetoshi
the Department of Information and Media, the University of Kitakyushu
-
Fu Ning
The Department Of Information And Media The University Of Kitakyushu:the Jedat Innovation Inc.
-
Takashima Youichi
The Department Of Information And Media The University Of Kitakyushu
-
Nakatake Shigetoshi
Department Of Information And Media Engineering The University Of Kitakyushu
関連論文
- Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
- Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
- Universal Graphs for Graphs with Bounded Path-Width
- On the Proper-Path-Decomposition of Trees
- The Oct-Touched Tile : A New Architecture for Shape-Based Routing( Analog Circuit Techniques and Related Topics)
- A Device-Level Placement with Schema Based Clusters in Analog IC Layouts(Analog Layout)(VLSI Design and CAD Algorithms)
- A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects(Physical Design)(VLSI Design and CAD Algorithms)
- Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints(Floorplan)(VLSI Design and CAD Algorithms)
- The 3D-Packing by Meta Data Structure and Packing Heuristics(Special Section on Discrete Mathematics and Its Applications)
- A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os(Discrete Mathematics and Its Applications)
- Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
- Digital Watermarking Technique for Motion Pictures Based on Quantization(Special Section on Cryptography and Information Security)
- Improved Digital Watermark Robustness against Translation and / or Cropping of an Image Area(Special Section on Cryptography and Information Security)
- Computational Complexity Analysis of Set-Bin-Packing Problem(Special Section on Discrete Mathematics and Its Applications)
- Recovery from Marked Altered Consciousness in a Patient with Adult-onset Type II Citrullinemia Diagnosed by DNA Analysis and Treated with a Living Related Partial Liver Transplantation
- Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk
- Routability of FPGAs with Extremal Switch-Block Structures(Special Section on Discrete Mathematics and Its Applications)
- An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm
- An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut
- Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan(Special Section on Discrete Mathematics and Its Applications)
- A transistor-level symmetrical layout generation method for analog device (VLSI設計技術)