Computational Complexity Analysis of Set-Bin-Packing Problem(Special Section on Discrete Mathematics and Its Applications)
スポンサーリンク
概要
- 論文の詳細を見る
The packing problem is to pack given items into given containers as efficiently as possible under various constraints. It is fundamental and significant with variations and applications. The Set-Bin-Packing(SBP)is a class of packing problems:Pack given items into as few bins which have the same capacity where every item is a set and a bin can contain items as long as the number of distinct elements in the union of the items equals to or less than the capacity. One of applications is in FPGA technology mapping, which is our initial motivation. In this paper, the computational complexity of SBP is studied with respect to three parameters α, γ, and δ which are the capacity, the upper bound of the number of elements in an item, and the upper bound of the number of items having an element, respectively. In contrast that the well known Integer-Bin-Packing(IBP)is NP-hard but is proved that even a simplest heuristics First-Fit-Decreasing(FFD)outputs exact solutions as long as α≦6, our result reveals that SBP remains NP-hard for a small values of these parameters. The results are summarized on a 3D map of computational complexities with respect to these three parameters.
- 1998-05-25
著者
-
Kajitani Y
Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
Kajitani Yoji
The Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
Takahashi Atsushi
The Department Of Gastoroenterology Kushiro Medical Association Hospital
-
Izumi T
Kyoto Univ. Kyoto‐shi Jpn
-
Izumi Tomonori
The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive
-
YOKOMARU Toshihiko
the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
-
Yokomaru Toshihiko
The Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
Takahashi Atsushi
The Department Of Communications And Integrated Systems Tokyo Institute Of Technology
関連論文
- Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
- Universal Graphs for Graphs with Bounded Path-Width
- On the Proper-Path-Decomposition of Trees
- The Oct-Touched Tile : A New Architecture for Shape-Based Routing( Analog Circuit Techniques and Related Topics)
- A Device-Level Placement with Schema Based Clusters in Analog IC Layouts(Analog Layout)(VLSI Design and CAD Algorithms)
- Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints(Floorplan)(VLSI Design and CAD Algorithms)
- LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression(Special Section on VLSI Design and CAD Algorithms)
- Computational Complexity Analysis of Set-Bin-Packing Problem(Special Section on Discrete Mathematics and Its Applications)
- Transcatheter Arterial Embolization for Impending Rupture of an Isolated Internal Iliac Artery Aneurysm Complicated with Disseminated Intravascular Coagulation
- Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk
- Routability of FPGAs with Extremal Switch-Block Structures(Special Section on Discrete Mathematics and Its Applications)
- Malignant Intestinal Schwannoma: A Case Report and a Review of the Literature in Japan
- Undifferentiated Carcinoma in the Cardioesophageal Junction which Produces Parathyroid Hormone Related Protein
- An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm
- An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut
- Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan(Special Section on Discrete Mathematics and Its Applications)
- Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture (Special Section on VLSI Design and CAD Algorithms)
- A Practical Clock Tree Synthesis for Semi-Synchronous Circuits(Special Section on VLSI Design and CAD Algorithms)
- Clock Schedule Design for Minimum Realization Cost (Special Section on VLSI Design and CAD Algorithms)
- A-3-3 単層プリント基板配線のための各ネットの配線長達成性を考慮した等長配線手法(A-3.VLSI設計技術,一般セッション)
- 一般同期方式における最適2クラスタ分割手法
- 遅延ばらつき適応回路 : 遅延ばらつき状況下の高性能回路
- FPGA上に実現した可変レイテンシ回路の性能評価(再構成回路,システムオンシリコンを支える設計技術)
- FOREWORD
- A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization
- 動的遅延分布の高速な見積もり手法(システムLSIの応用と要素技術,プロセッサ,DSP,画像処理技術及び一般)
- 動的遅延分布の高速な見積もり手法(システムLSIの応用と要素技術,プロセッサ,DSP,画像処理技術及び一般)
- 動的遅延分布の高速な見積もり手法(システムLSIの応用と要素技術,プロセッサ,DSP,画像処理技術及び一般)
- 動的遅延分布の高速な見積もり手法(システムLSIの応用と要素技術,プロセッサ,DSP,画像処理技術及び一般)
- A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization
- エラー検出回復方式を用いた可変レイテンシ回路のための高速な性能見積もり手法(低電力化・高信頼化,組込み技術とネットワークに関するワークショップETNET2013)
- 単層プリント基板のための各ネットの目標配線長達成性を考慮した配線手法(配線設計,システムオンシリコンを支える設計技術)
- A-3-6 指定長幹配線間題において配線長を調整する領域に関する一考察(A-3.VLSI設計技術)
- 半正定値緩和法を用いた LELECUT トリプルパターニングのためのレイアウト分割手法
- 側壁ダブルパターニングのための修正2色グリッド配線法 (VLSI設計技術)
- ダブルパターニングにおけるリソグラフィECOのためのパターン局所修正法 (VLSI設計技術)
- エラー検出回復方式を用いた可変レイテンシ回路のための高速な性能見積もり手法(低電力化・高信頼化,組込み技術とネットワークに関するワークショップETNET2013)
- 集合対間配線に対する配線長差削減アルゴリズムの改良 (VLSI設計技術)
- FPGA上に実現した可変レイテンシ回路の性能評価