A Device-Level Placement with Schema Based Clusters in Analog IC Layouts(Analog Layout)(<Special Section>VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
A challenge to an automated layout of analog ICs starts with the insight into high quality placements crafted by experts. We observe first that matched devices or elemental functions such as input, output, amplifiers, etc are clustered. Second, devices in the same cluster are located faithfully to the drawn schema. Third, these two features are simultaneously fulfilled in a well-compacted placement. This paper proposes a novel device-level placement that simulates the above features based on Sequence-Pair. A slight modification of the meaning, say, of relation "A is left-of B" to relation "A is not right-of B" enlarges the freedom and allows a neater compaction of clusters allowing zigzag border curves. As the consequence, clusters are placed faithfully to relative position in the schema. We tested our algorithm for industrial instances and compared results with those by manual design. The results showed better features in performance figures than the those of manual designs by, on average, 13.5% and 21.2% with respect to the area and total net-length.
- 社団法人電子情報通信学会の論文
- 2004-12-01
著者
-
Takashima Yasuhiro
The Department Of Information And Media The University Of Kitakyushu
-
Takashima Yasuhiro
The Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
Nakatake S
The Department Of Information And Media The University Of Kitakyushu
-
Kajitani Y
Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
Kajitani Yoji
The Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
-
NOJIMA Takashi
Research and Development Division, Jedat Innovation Inc.
-
ZHU Xiaoke
Research and Development Division, Jedat Innovation Inc.
-
TAKASHIMA Yasuhiro
Dept. of Information and Media Sciences, The University of Kitakyushu
-
NAKATAKE Shigetoshi
Dept. of Information and Media Sciences, The University of Kitakyushu
-
KAJITANI Yoji
Dept. of Information and Media Sciences, The University of Kitakyushu
-
Takashima Youichi
The Department Of Information And Media The University Of Kitakyushu
-
Zhu Xiaoke
Research And Development Division Jedat Innovation Inc.
-
Nojima Takashi
Research And Development Division Jedat Innovation Inc.:dept. Of Information And Media Sciences The
-
Nakatake Shigetoshi
Department Of Information And Media Engineering The University Of Kitakyushu
関連論文
- Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
- Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
- Universal Graphs for Graphs with Bounded Path-Width
- On the Proper-Path-Decomposition of Trees
- The Oct-Touched Tile : A New Architecture for Shape-Based Routing( Analog Circuit Techniques and Related Topics)
- A Device-Level Placement with Schema Based Clusters in Analog IC Layouts(Analog Layout)(VLSI Design and CAD Algorithms)
- A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects(Physical Design)(VLSI Design and CAD Algorithms)
- Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints(Floorplan)(VLSI Design and CAD Algorithms)
- The 3D-Packing by Meta Data Structure and Packing Heuristics(Special Section on Discrete Mathematics and Its Applications)
- A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os(Discrete Mathematics and Its Applications)
- Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
- Digital Watermarking Technique for Motion Pictures Based on Quantization(Special Section on Cryptography and Information Security)
- Improved Digital Watermark Robustness against Translation and / or Cropping of an Image Area(Special Section on Cryptography and Information Security)
- Computational Complexity Analysis of Set-Bin-Packing Problem(Special Section on Discrete Mathematics and Its Applications)
- Recovery from Marked Altered Consciousness in a Patient with Adult-onset Type II Citrullinemia Diagnosed by DNA Analysis and Treated with a Living Related Partial Liver Transplantation
- Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk
- Routability of FPGAs with Extremal Switch-Block Structures(Special Section on Discrete Mathematics and Its Applications)
- An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm
- An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut
- Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan(Special Section on Discrete Mathematics and Its Applications)
- A transistor-level symmetrical layout generation method for analog device (VLSI設計技術)