A transistor-level symmetrical layout generation method for analog device (VLSI設計技術)
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概要
- 論文の詳細を見る
This paper introduces a transistor-level symmetrical layout generation algorithm aiming at maximum diffusion-merging to the current paths for analog circuit. We present a SA-based algorithm to symmetrically assign the transistor pair into two rows and meanwhile minimize the total wirelength and diffusion gaps. Two examples are used to demonstrate the effectiveness of our algorithm.
- 社団法人電子情報通信学会の論文
- 2011-09-19
著者
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Yang Bo
Department Of Cardiology Key Laboratory Of Cardiovascular Remodeling And Function Research Chinese M
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Li Jing
Department Of Information And Media Engineering The University Of Kitakyushu
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Yang Bo
Department Of Information And Media Engineering The University Of Kitakyushu
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DONG Qing
Department of Information and Media Engineering, The University of Kitakyushu
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Dong Qing
Department Of Information And Media Engineering The University Of Kitakyushu
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Li Jing
Department Of Agriculture Faculty Of Agriculture Kochi University
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Nakatake Shigetoshi
Department Of Information And Media Engineering The University Of Kitakyushu
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Yang Bo
Univ. Kitakyusyu Fukuoka Jpn
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Shigetoshi Nakatake
The University of Kitakyushu
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Shigetoshi Nakatake
Department of Information and Media Engineering, The University of Kitakyushu
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