A transistor-level symmetrical layout generation method for analog device (VLSI設計技術)

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概要

• 論文の詳細を見る
• 電子情報通信学会の論文
• 2011-09-26

著者

• Li Jing

  Department Of Information And Media Engineering The University Of Kitakyushu

• Yang Bo

  Univ. Kitakyushu Kitakyushu Jpn

• Dong Qing

  Department Of Information And Media Engineering The University Of Kitakyushu

関連論文

• A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion
• Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
• A transistor-level symmetrical layout generation method for analog device (VLSI設計技術)
• A transistor-level symmetrical layout generation method for analog device (VLSI設計技術)

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