Structured Placement with Topological Regularity Evaluation

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概要

• 論文の詳細を見る

• This paper introduces a new concept of regularity-oriented floorplanning and block placement-structured placement, it takes the regularity as a criterion of placement so as to improve the performance. We provide the methods to extract regular structures from a placement representation in linear time, and manage to evaluate these structures by quantifying the regularity as an objective function. We also construct a particular simulated annealing framework, which optimizes placement topology and physical dimension separately and alternately so that it attains a solution balancing the trade-off between regularity and area efficiency. Furthermore, we introduce the symmetry-oriented structured placement to produce symmetrical placement. Experiments show that the resultant placements achieve regularity without increased chip area and wire length, compared to those by existing methods.

• 一般社団法人情報処理学会の論文
• 2009-08-14

著者

• Shigetoshi Nakatake

  The University of Kitakyushu

• Qing Dong

  The University of Kitakyushu

• Shigetoshi Nakatake

  Department of Information and Media Engineering, The University of Kitakyushu

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• A transistor-level symmetrical layout generation method for analog device (VLSI設計技術)
• Structured Placement with Topological Regularity Evaluation

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