LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression(Special Section on VLSI Design and CAD Algorithms)

概要

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In this paper, a design of Programmable Logic Device(PLD)and a synthesis approach are proposed. Our PLD is derived from traditional Programmable Logic Array(PLA). The key extension is that programmable AND devices in PLA is replaced by Look-Up Tables(LUTs). A series of cascaded LUTs in the array can generate more complex terms, which we call generalized complex terms(GCTs), than product terms. In order to utilize the capability, a synthesis approach to map a given function into the array is also proposed. Our approach generates a expression of the sum of GCTs aiming to minimize the number of terms. A number of experimental results demonstrate that the number of terms for our PLD generated by our approach is 14.9% fewer than that by an existing approach. We design our PLD based on a fundamental unit named ηGCT cell which can be used as LUTs in multiple sizes or random access memories. Implementation of the PLD based on a fundamental unit named nGCT cell which can be used as LUTs or random access memories is also described.
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2001-11-01