Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits(System Level Design,<Special Section>VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algorithm analyzes the pipelined circuit and determines the intermediate registers that can be removed. An efficient subsidiary algorithm is presented that computes the minimum feasible clock period of a circuit containing multi-clock cycle paths. Experiments with a pipelined adder and multiplier verify that the proposed algorithm can reduce the number of intermediate registers without degrading performance, even when delay variations exist.
- 一般社団法人電子情報通信学会の論文
- 2006-12-01
著者
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Takahashi Atsushi
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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Takahashi Atsushi
Department Of Cardiology Akita City General Hospital
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Takahashi Atsushi
Graduate School Of Engineering Osaka University
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Takahashi Atsushi
Faculty of Engineering, Tokyo Institute of Technology
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ROSDI Bakhtiar
Department of Communications and Integrated Systems, Tokyo Institute of Technology
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Takahashi Atsushi
Departmant Of Surgery(i) Kanazawa University School Of Medicine
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Rosdi Bakhtiar
Tokyo Inst. Of Technol. Tokyo Jpn
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Rosdi Bakhtiar
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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