Post-Silicon Clock-Timing Tuning Based on Statistical Estimation

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概要

• 論文の詳細を見る

• In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs clock timing and presuming the rest of FFs clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.

• （社）電子情報通信学会の論文
• 2008-09-01

著者

• Takashima Yasuhiro

  Faculty Of Environmental Engineering The University Of Kitakyushu

• NAKAMURA Yuichi

  System IP Core Research Laboratories, NEC

• HASHIZUME Yuko

  Faculty of Environmental Engineering, the University of Kitakyushu

• Hashizume Yuko

  Faculty Of Environmental Engineering The University Of Kitakyushu

• Nakamura Yuichi

  System Ip Core Research Lab. Nec

• Nakamura Yuichi

  System Ip Core Res. Laboratories Nec Corp.

関連論文

• A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os(Discrete Mathematics and Its Applications)
• Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
• Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
• A Verification and Analysis Tool Set for Embedded System Design
• Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems

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