A Verification and Analysis Tool Set for Embedded System Design
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概要
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This paper presents a verification and analysis tool set for embedded systems. Recently, the development scale of embedded systems has been increasing since they are used for mobile systems, automobile platforms, and various consumer systems with rich functionality. This has increased the amount of time and cost needed to develop them. Consequently, it is very important to develop tools to reduce development time and cost. This paper describes a tool set consisting of three tools to enhance the efficiency of embedded system design. The first tool is an integrated tool platform. The second is a remote debugging system. The third is a clock-accurate verification system based on a field-programmable gate array (FPGA) for custom embedded systems. This tool set promises to significantly reduce the time and cost needed to develop embedded systems.
- 2011-12-01
著者
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Nakamura Yuichi
System Ip Core Research Lab. Nec
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Nakamura Yuichi
System Ip Core Research Laboratories Nec Corp.
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Nakamura Yuichi
System Ip Core Res. Laboratories Nec Corp.
関連論文
- Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
- Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
- A Verification and Analysis Tool Set for Embedded System Design
- Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems