Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements(Circuit Synthesis,<Special Section>VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.
- 一般社団法人電子情報通信学会の論文
- 2007-12-01
著者
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Takahashi Atsushi
Department Of Cardiology Akita City General Hospital
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Takahashi Atsushi
Graduate School Of Engineering Osaka University
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Takahashi Atsushi
Faculty of Engineering, Tokyo Institute of Technology
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ROSDI Bakhtiar
Department of Communications and Integrated Systems, Tokyo Institute of Technology
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Takahashi Atsushi
Departmant Of Surgery(i) Kanazawa University School Of Medicine
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Rosdi Bakhtiar
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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