A-3-4 Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework
スポンサーリンク
概要
- 論文の詳細を見る
- 社団法人電子情報通信学会の論文
- 2006-03-08
著者
-
Takahashi Atsushi
Tokyo Inst. Technol. Tokyo Jpn
-
Takahashi Atsushi
Graduate School Of Engineering Osaka University
-
Takahashi Atsushi
Faculty of Engineering, Tokyo Institute of Technology
-
Kohira Yukihide
Tokyo Inst. Technol. Tokyo Jpn
-
Kohira Yukihide
Tokyo Institute Of Technology Dept. Of Communications And Integrated Systems
-
Takahashi Atsushi
Tokyo Institute Of Technology Dept. Of Communications And Integrated Systems
-
Takahashi Atsushi
Tokyo Inst. Of Technol. Tokyo Jpn
関連論文
- A-3-10 Top Layer Plating Lead Maximization for BGA Packages
- PE-201 Vector-projected 187-channel Electrocardiogram can Evaluate an Alternance of T-wave Current Density and Disptribution(PE034,ECG/Body Surface Potential Mapping/Holter (A),Poster Session (English),The 73rd Annual Scientific Meeting of The Japanese Ci
- A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees(Special Section on VLSI Design and CAD Algorithms)
- Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages
- MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages
- A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework
- Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound
- Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
- Universal Graphs for Graphs with Bounded Path-Width
- Schedule-Clock-Tree Routing for Semi-Synchronous Circuits (Special Section on VLSI Design and CAD Algorithms)
- Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
- CAFE Router : A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles
- A Fast Clock Scheduling for Peak Power Reduction in LSI
- Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
- A-3-4 Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework
- A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages(Discrete Mathematics and Its Applications)
- Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages
- Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages(Physical Design,VLSI Design and CAD Algorithms)
- Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- A Semi-Synchronous Circuit Design Method by Clock Tree Modification(Special Section on VLSI Design and CAD Algorithms)
- Clock Schedule Design for Minimum Realization Cost (Special Section on VLSI Design and CAD Algorithms)
- Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion (Special Section on VLSI Design and CAD Algorithms)
- Cost-Radius Balanced Spanning/Steiner Trees (Special Section on Discrete Mathematics and Its Applications)
- Practical Fast Clock-Schedule Design Algorithms(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements(Circuit Synthesis,VLSI Design and CAD Algorithms)
- Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits(System Level Design,VLSI Design and CAD Algorithms)
- Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages (デザインガイア2006--VLSI設計の新しい大地を考える研究会)
- Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages (デザインガイア2006--VLSI設計の新しい大地を考える研究会)
- FOREWORD