Cost-Radius Balanced Spanning/Steiner Trees (Special Section on Discrete Mathematics and Its Applications)
スポンサーリンク
概要
- 論文の詳細を見る
The most crucial factor that degrades a high-speed VLSI is the signal propagation delay in a routing tree. It is estimated by the sum of the delay caused by the source-to-sink path length and by the total length. To design a routing tree in which these two are both small and balanced, we propose an algorithm to construct such a spanning tree, based on the idea of constructing a tree combining the minimum-spanning-tree and shortest-path-tree algorithms. This idea is extended to finding a rectilinear Steiner tree. Experiments are presented to illustrate how the source-to-sink path length and total length can be balanced and small.
- 一般社団法人電子情報通信学会の論文
- 1997-04-25
著者
-
Kajitani Yoji
Faculty Of Engineering Tokyo Institute Of Technology
-
Takahashi Atsushi
Graduate School Of Engineering Osaka University
-
Takahashi Atsushi
Faculty of Engineering, Tokyo Institute of Technology
-
Mitsubayashi Hideki
Faculty Of Engineering Tokyo Institute Of Technology
-
Takahashi Atsushi
Faculty Of Engineering Tokyo Institute Of Technology
関連論文
- A-3-10 Top Layer Plating Lead Maximization for BGA Packages
- A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees(Special Section on VLSI Design and CAD Algorithms)
- Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages
- MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages
- Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound
- Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
- Universal Graphs for Graphs with Bounded Path-Width
- A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os(Discrete Mathematics and Its Applications)
- Schedule-Clock-Tree Routing for Semi-Synchronous Circuits (Special Section on VLSI Design and CAD Algorithms)
- Recognition of Floorplan by Parametric BSG for Reuse of Layout Design
- Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
- CAFE Router : A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles
- A Fast Clock Scheduling for Peak Power Reduction in LSI
- Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
- A-3-4 Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework
- A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages(Discrete Mathematics and Its Applications)
- Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages
- Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages(Physical Design,VLSI Design and CAD Algorithms)
- Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- A Semi-Synchronous Circuit Design Method by Clock Tree Modification(Special Section on VLSI Design and CAD Algorithms)
- Clock Schedule Design for Minimum Realization Cost (Special Section on VLSI Design and CAD Algorithms)
- Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion (Special Section on VLSI Design and CAD Algorithms)
- Cost-Radius Balanced Spanning/Steiner Trees (Special Section on Discrete Mathematics and Its Applications)
- Practical Fast Clock-Schedule Design Algorithms(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements(Circuit Synthesis,VLSI Design and CAD Algorithms)
- Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits(System Level Design,VLSI Design and CAD Algorithms)
- Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages (デザインガイア2006--VLSI設計の新しい大地を考える研究会)
- Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages (デザインガイア2006--VLSI設計の新しい大地を考える研究会)
- Derivative Coupling Meson Theory and PCAC
- Current Commutation Relation and Pion-Nucleon Scattering
- The high mannose-type glycan binding lectin actinohivin : dimerization greatly improves anti-HIV activity
- Actinohivin : specific amino acid residues essential for anti-HIV activity
- (1,0,x)-Representation of a Graph (Graphs and Combinatorics III)
- FOREWORD