A Semi-Synchronous Circuit Design Method by Clock Tree Modification(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.

• 社団法人電子情報通信学会の論文
• 2002-12-01

著者

• Takahashi Atsushi

  Graduate School Of Engineering Osaka University

• Ishijima Seiichiro

  Graduate School Of Science And Technology Tokyo Institute Of Technology:(present Address)nec Electro

• UTSUMI Tetsuaki

  Graduate School of Science and Technology, Tokyo Institute of Technology

• OTO Tomohiro

  Graduate School of Science and Technology, Tokyo Institute of Technology

• Oto Tomohiro

  Graduate School Of Science And Technology Tokyo Institute Of Technology:(present Address)sony Comput

• Utsumi Tetsuaki

  Graduate School Of Science And Technology Tokyo Institute Of Technology:(present Address)toshiba Cor

• Takahashi Atsushi

  Graduate School Of Science And Technology Tokyo Institute Of Technology

• Takahashi Atsushi

  Graduate School Of Engineering Osaka Univ.

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• FOREWORD

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