Evaluation of Digitally Controlled PLL by Clock-Period Comparison(<Special Section>Analog Circuits and Related SoC Integration Technologies)

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概要

• 論文の詳細を見る

• For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.

• 社団法人電子情報通信学会の論文
• 2007-06-01

著者

• Sano Eiichi

  Research Center For Integrated Quantum Electronics Hokkaido University

• IKEBE Masayuki

  Graduate School of Information Science and Technology, Hokkaido University

• MAKIHARA Yukinobu

  Graduate School of Information Science and Technology, Hokkaido University

• Makihara Yukinobu

  Graduate School Of Information Science And Technology Hokkaido University

• Sano Eiichi

  Research Center For Integrated Quantum Electronics (rciqe) Hokkaido University

• Ikebe Masayuki

  Graduate School Of Information Science And Technology Hokkaido University

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