A Practical Analog BIST Cooperated with an LSI Tester(<Special Section> Analog Circuit Techniques and Related Topics)
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概要
- 論文の詳細を見る
This paper proposes a new approach for analog portion testing, which can meet requirements for high-speed and high-accuracy testing simultaneously with reasonable cost. The key concept of the new method is cooperation of an LSI tester and some circuitry built in a target SoC device. We will explain the operation principle of the proposed method. The proposed method can be one of the methods to overcome today's expensive production test of analog portion on SoC (System on Chip) devices which heavily depends on LSI tester capability and will become harder in near future.
- 社団法人電子情報通信学会の論文
- 2006-02-01
著者
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Kobayashi Haruo
Electronic Engineering Department Graduate School Of Engineering Gunma University
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Kobayashi Haruo
The Department Of Electronic Engineering Faculty Of Engineering Gunma University
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Kobayashi Haruo
Sanyo Lsi Design-system Soft Co. Ltd.
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Hayasaka Naoto
The Department Of Electronic Engineering Faculty Of Engineering Gunma University
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Kobayashi H
The Department Of Electronic Engineering Faculty Of Engineering Gunma University
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Kobayashi Haruo
The Department Of Electrical Engineering Tokyo Metropolitan College Of Technology
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KOMURO Takanori
Agilent Technologies International Japan, Ltd.
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SAKAYORI Hiroshi
Agilent Technologies International Japan, Ltd.
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Komuro T
Agilent Technologies International Japan Ltd.
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Komuro Takanori
Department Of Electronic Engineering Faculty Of Engineering Gunma University
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Sakayori Hiroshi
Agilent Technologies International Japan Ltd.
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Komuro Takanori
Agilent Technologies International Japan Ltd.
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- FOREWORD
- Dynamic Power Dissipation of Track / Hold Circuit